August 27, 1998
GENERAL RELEASE SPECIFICATION
5.4.3 Core Timer
A reset has the following effects on the Core Timer:
•
•
Clears the Core Timer counter register (CTCR).
Clears the Core Timer interrupt flag and enable bits in the Core Timer
status and control register (CTSCR).
•
Sets the real-time interrupt rate selection bits (RT0, RT1) such that the
device will start with the longest real-time interrupt and COP timeout
delays.
5.4.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
5.4.5 16-Bit Programmable Timer
A reset has the following effects on the 16-bit programmable Timer:
•
•
•
Initializes the timer counter registers (TMRH, TMRL) to a value of
$FFFC.
Initializes the alternate timer counter registers (ACRH, ACRL) to a value
of $FFFC.
Clears all the interrupt enables and the output level bit (OLVL) in the
timer control register (TCR).
•
•
•
•
Does not affect the input capture edge bit (IEDG) in the TCR.
Does not affect the interrupt flags in the timer status register (TSR).
Does not affect the input capture registers (ICRH, ICRL).
Does not affect the output compare registers (OCRH, OCRL).
5.4.6 SM-Bus Serial Interface
A reset has the following effects on the SM-Bus serial interface:
•
•
•
•
•
Clears all bits in the address register (SMADR) and those
unimplemented bit locations are not affected.
Clears all bits in the frequency divider register (SMFDR) and those
unimplemented bit locations are not affected.
Clears all bits in control register (SMCR) and those unimplemented bit
locations are not affected.
Sets SMCF & RXAK bits and clears other bits and those unimplemented
bit locations are not affected.
Does not affect the contents of the data I/O register (SMDR).
MC68HC05SB7
REV 2.1
RESETS
MOTOROLA
5-5
FREESCALE [ Freescale ]
