GENERAL RELEASE SPECIFICATION
August 27, 1998
5.1
POWER-ON RESET
A positive transition on the V
pin generates a power-on reset. The power-on
DD
reset is strictly for conditions during powering up and cannot be used to detect
drops in power supply voltage.
A 4064 t
(internal clock cycle) delay after the oscillator becomes active allows
CYC
the clock generator to stabilize. If the RESET pin is at logic zero at the end of the
multiple t time, the MCU remains in the reset condition until the signal on the
CYC
RESET pin goes to a logic one.
5.2
EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5t
generates an external reset.
CYC
This pin is connected to a Schmitt trigger input gate to provide and upper and
lower threshold voltage separated by a minimum amount of hysteresis. The exter-
nal reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the internal RST signal that resets the CPU and peripher-
als.
The RESET pin can also act as an open drain output. It will be pulled to a low
state by an internal pulldown device that is activated by three internal reset
sources. This RESET pulldown device will only be asserted for 3 - 4 cycles of the
internal clock, f , or as long as the internal reset source is asserted. When the
OP
external RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to V , as this may overload some power
DD
supply designs when the internal pulldown on the RESET pin activates.
5.3
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
COP Watchdog timer reset, the low voltage reset, and the illegal address detector.
Only the COP Watchdog timer reset, low voltage reset and illegal address detec-
tor will also assert the pulldown device on the RESET pin for the duration of the
reset function or 3 - 4 internal clock cycles, whichever is longer.
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 4064 internal processor bus clock cycles after the oscillator becomes
active.
MOTOROLA
5-2
RESETS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
