August 27, 1998
GENERAL RELEASE SPECIFICATION
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 4064 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. V
must drop
DD
below V
in order for the internal POR circuit to detect the next rise of V .
POR
DD
5.3.2 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic zero to the COPC bit of the COP register at location $1FF0.
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
COPR
$1FF0
R
0
COPC
0
W
reset:
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 5-2. COP Watchdog Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = No effect on system.
0 = Reset COP watchdog timer.
The COP Watchdog reset will assert the pulldown device to pull the RESET pin
low for three to four clock cycles of the internal bus clock.
After a POR or reset, the COP watchdog is disabled. It is enabled b writing a logic
“1” to the COPON bit in the Miscellaneous Control Register (see Figure 5-2).
Once enabled, the COP watchdog can only be disabled by a POR or reset.
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
U = UNAFFECTED BY RESET
Figure 5-3. Miscellaneous Control Register (MCR)
COPON — COP ON
COPON is a write-once bit.
1 = Enables COP watchdog system.
0 = No effect on system.
See section on Core Timer for detail on COP watchdog timeout periods.
MC68HC05SB7
REV 2.1
RESETS
MOTOROLA
5-3
FREESCALE [ Freescale ]
