GENERAL RELEASE SPECIFICATION
August 27, 1998
IRQE — External Interrupt Request Enable
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt processing enabled.
0 = External interrupt processing disabled.
VCOEN — VCO Enable
Please refer to section on System Clock.
LEVEL — External Interrupt Sensitivity
This bit makes the external interrupt inputs level-triggered as well as edge-trig-
gered.
1 = IRQ/V pin negative edge-triggered and low level-triggered.
PP
0 = IRQ/V pin negative edge-triggered only.
PP
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external interrupt
request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending.
0 = No interrupt request pending.
The following condition set the IRQ flag:
•
An external interrupt signal on the IRQ/V pin.
PP
The following conditions clear the IRQ flag:
•
•
When the CPU fetches the interrupt vector.
When a logic “1” is written to the IRQR bit.
IRQR — Interrupt Request Reset
This write-only bit clears the IRQF flag bit and prevents redundant execution of
interrupt routines. Writing a logic one to IRQR clears the IRQF. Writing a logic
zero to IRQR has no effect. IRQR always reads as a logic zero. Reset has no
affect on IRQR.
1 = Clear IRQF flag bit.
0 = No effect.
4.5
CORE TIMER INTERRUPTS
The Core Timer can generate the following interrupts:
•
•
Timer overflow interrupt.
Real-time interrupt.
Setting the I bit in the condition code register disables Core Timer interrupts. The
controls and flags for these interrupts are in the Core Timer status and control reg-
ister (CTSCR) located at $0008.
MOTOROLA
4-6
INTERRUPTS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
