August 27, 1998
GENERAL RELEASE SPECIFICATION
V
TO
PP
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/V
PP
V
DD
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
RST
IRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-3. External Interrupt Logic
4.4.2 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4, contains an
external interrupt mask (IRQE), an external interrupt flag (IRQF), and a flag reset
bit (IRQR). Unused bits will read as logic zeros. Reset sets the IRQE bit and
clears all the other bits.
BIT 7
IRQE
1
BIT 6
VCOEN
1
BIT 5
LEVEL
0
BIT 4
0
BIT 3
IRQF
BIT 2
0
BIT 1
0
BIT 0
0
ISCR
R
$000D
W
IRQR
0
reset:
0
0
0
0
Figure 4-4. IRQ Status and Control Register (ISCR)
MC68HC05SB7
REV 2.1
INTERRUPTS
MOTOROLA
4-5
FREESCALE [ Freescale ]
