GENERAL RELEASE SPECIFICATION
August 27, 1998
4.3
4.4
SOFTWARE INTERRUPT
The software interrupt (SWI) instruction causes a nonmaskable interrupt.
EXTERNAL INTERRUPT
The IRQ/V pin is the source that generates external interrupt. Setting the I bit in
PP
the condition code register or clearing the IRQE bit in the interrupt status and con-
trol register disables this external interrupt.
4.4.1 IRQ/V Pin
PP
An interrupt signal on the IRQ/V pin latches an external interrupt request. To
PP
help clean up slow edges, the input from the IRQ/V
pin is processed by a
PP
Schmitt trigger gate. When the CPU completes its current instruction, it tests the
IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit
is clear and the IRQE bit is set, then the CPU begins the interrupt sequence. The
CPU clears the IRQ latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can recognize
the new interrupt request. Figure 4-3 shows the logic for external interrupts.
NOTE
If the IRQ/V pin is not in use, it should be connected to the V pin.
PP
DD
The IRQ/V pin can be negative edge-triggered only or negative edge- and low-
PP
level-triggered. External interrupt sensitivity is programmed with the LEVEL bit.
With the edge- and level-sensitive trigger option, a falling edge or a low level on
the IRQ/V pin latches an external interrupt request. The edge- and level-sensi-
PP
tive trigger option allows connection to the IRQ/V pin of multiple wired-OR inter-
PP
rupt sources. As long as any source is holding the IRQ/V
low, an external
PP
interrupt request is present, and the CPU continues to execute the interrupt ser-
vice routine.
With the edge-sensitive-only trigger option, a falling edge on the IRQ/V
pin
PP
latches an external interrupt request. A subsequent interrupt request can be
latched only after the voltage level on the IRQ/V pin returns to a logic one and
PP
then falls again to logic zero.
MOTOROLA
4-4
INTERRUPTS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
