GENERAL RELEASE SPECIFICATION
August 27, 1998
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of the
higher priority interrupt first. A higher priority interrupt does not actually interrupt a
lower priority interrupt service routine unless the lower priority interrupt service
routine clears the I bit.
4.2
INTERRUPT PROCESSING
The CPU does the following actions to begin servicing an interrupt:
•
•
•
Stores the CPU registers on the stack in the order shown in Figure 4-1.
Sets the I bit in the condition code register to prevent further interrupts.
Loads the program counter with the contents of the appropriate interrupt
vector locations as shown in Table 4-1.
The return from interrupt (RTI) instruction causes the CPU to recover its register
contents from the stack as shown in Figure 4-1. The sequence of events caused
by an interrupt are shown in the flow chart in Figure 4-2.
$0020
$0021
(BOTTOM OF RAM)
$00BE
$00BF
$00C0
$00C1
$00C2
(BOTTOM OF STACK)
UNSTACKING
ORDER
n
n+1
n+2
CONDITION CODE REGISTER
ACCUMULATOR
5
4
3
2
1
1
2
3
4
5
INDEX REGISTER
n+3 PROGRAM COUNTER (HIGH BYTE)
n+4
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
$00FD
$00FE
$00FF
TOP OF STACK (RAM)
Figure 4-1. Interrupt Stacking Order
MOTOROLA
4-2
INTERRUPTS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
