Freescale Semiconductor, Inc.
Parallel Input/Output
Port B
7.4.5 PB0, PBI, PB2 a nd PB3 Log ic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and
PB3 pins of port B. When these port B pins are programmed as an
output, reading the port bit actually reads the value of the data latch and
not the voltage on the pin itself. When these port B pins are programmed
as an input, reading the port bit reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its DDRB bit.
The operations of the PB0:3 pins are summarized in Table 7-2.
READ $0005
WRITE $0005
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
(PINS PB0, PB1, PB2, PB3)
DATA DIRECTION
REGISTER B
BIT DDRBx
R
PORT BDATA
REGISTER
BIT PBx
WRITE $0001
PBx
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIBx
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-8. PB0:3 Pin I/O Circuit
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
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