Freescale Semiconductor, Inc.
Pa ra lle l Inp ut/ Outp ut
7.4.3 Pulld own Re g iste r B (PDRB)
All port B pins can have software programmable pulldown devices
enabled or disabled globally by the SWPDI bit in the MOR. These
pulldown devices are individually controlled by the write-only pulldown
register B (PDRB) shown in Figure 7-7. Clearing the PDIB7–PDIB0 bits
in the PDRB turns on the pulldown devices if the port B pin is an input.
Reading the PDRB returns undefined results since it is a write-only
register. Reset clears the PDIB7–PDIB0 bits, which turns on all the port
B pulldown devices.
$0011
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PDIB7
0
PDIB6
0
PDIB5
0
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
0
DIB0
0
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
PDIB7–PDIB0 — Port B Pulldown Inhibit Bits
Writing to these write-only bits controls the port B pulldown devices.
Reading these pulldown register B bits returns undefined data. Reset
clears bits PDIB7–PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on if pin has
been programmed by the DDRB to be an input
7.4.4 Port B Log ic
All port B pins have the general I/O port logic similar to port A; but they
also share this function with inputs or outputs from other modules, which
are also attached to the pin itself or override the general I/O function.
PB0, PB1, PB2, and PB3 simply share their inputs with another module.
PB4, PB5, PB6, and PB7 will have their operation altered by outputs or
controls from other modules.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
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