Freescale Semiconductor, Inc.
Pa ra lle l Inp ut/ Outp ut
7.4 Port B
Port B is an 8-bit, general-purpose bidirectional I/O port with the
following features:
• Programmable pulldown devices
• PB0–PB4 are shared with the analog subsystem
• PB3 and PB4 are shared with the 16-bit programmable timer
• PB4 can be driven directly by the output of comparator 1
• PB5–PB7 are shared with the simple serial interface (SIOP)
• High current sinking capability on the PB4 pin
• High current sourcing capability on the PB4 pin
7.4.1 Port B Da ta Re g iste r (PORTB)
The port B data register contains a bit for each of the port B pins. When
a port B pin is programmed to be an output, the state of its data register
bit determines the state of the output pin. When a port B pin is
programmed to be an input, reading the port B data register returns the
logic state of the pin. Reset has no effect on port B data.
$0001
Read:
Bit 7
PB7
6
5
4
3
2
1
Bit 0
PB0
PB6
PB5
PB4
PB3
PB2
PB1
Write:
Reset:
Unaffected by Reset
Alternate:
Alternate:
Alternate:
SCK
SCK
SCK
SDI
SDI
SDI
SDO
SDO
SDO
AN4
AN3
TCAP
TCAP
AN2
AN2
AN2
AN1
AN1
AN1
AN0
AN0
AN0
TCMP
CMP1
Figure 7-5. Port B Data Register (PORTB)
PB0-PB7 — Port B Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register B. Reset has no effect on port B data.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
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