Freescale Semiconductor, Inc.
Parallel Input/Output
Port A
EXTERNAL
INTERRUPT
REQUEST
(PA0:3)
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
R
PORT A DATA
REGISTER
BIT PAx
U
WRITE $0000
PAx
A
T
A
HIGH SINK/SOURCE
CURRENT
CAPABILITY
READ $0000
WRITE $0010
I
PULLDOWN
REGISTER A
BIT PDIAx
PULLDOWN
DEVICE
R
RESET
MASK OPTION REGISTER ($1FF1)
Figure 7-4. Port A I/O Circuit
Table 7-1. Port A Pin Functions
PORTA Access
Port A
Result on
Port A
Pin(s)
SWPDI
(in MOR)
(Pin or Data Register)
Port A Pins
PDIAx
DDRAx*
Read
Write
Pulldown
Pin
PA0
PA1
PA2
PA3
PA4
PA5
0
0
1
X
0
0
Pin
Data
On
Off
Off
Off
PAx In
1
X
X
0
0
1
Pin
Pin
Data
Data
Data
PAx In
PAx In
Data
PAx Out
* DDRA can always be read or written.
X = Don’t care
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Parallel Input/Output
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