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68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Parallel Input/Output  
Port B  
7.4.2 Da ta Dire c tion Re g iste r B (DDRB)  
The contents of the port B data direction register (DDRB) determine  
whether each port B pin is an input or an output. Writing a logic one to a  
DDRB bit enables the output buffer for the associated port B pin. A  
DDRB bit set to a logic one also disables the pulldown device for that pin.  
Writing a logic zero to a DDRB bit disables the output buffer for the  
associated port B pin. A reset initializes all DDRB bits to logic zeros,  
configuring all port B pins as inputs.  
$0005  
Read:  
Write:  
Reset:  
Bit 7  
6
5
4
3
2
1
Bit 0  
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0  
0
0
0
0
0
0
0
0
Figure 7-6. Data Direction Register B (DDRB)  
DDRB7–DDRB0 — Port B Data Direction Bits  
These read/write bits control port B data direction. Reset clears the  
bits DDRB7–DDRB0.  
1 = Corresponding port B pin configured as output and pulldown  
device disabled  
0 = Corresponding port B pin configured as input  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
General Release Specification  
Parallel Input/Output  
For More Information On This Product,  
Go to: www.freescale.com  
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