Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the port A pins (PA0 thru PA7) to act as other IRQ interrupt sources. These
sources are all combined into a single ORing function to be latched by the IRQ
latch.
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the IRQ
pin or a port A pin if port A interrupts have been enabled. If edge-only sensitivity is
chosen by a mask option, only the IRQ latch output can activate a request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt
sensitive to the following cases:
1. Falling edge on the IRQ pin with all enabled port A interrupt pins at a
high level.
2. Falling edge on any enabled port A interrupt pin with all other enabled
port A interrupt pins and the IRQ pin at a high level.
If level sensitivity is chosen, the active high state of the IRQ input can also
activate an IRQ request to the CPU to generate the IRQ interrupt sequence. This
makes the IRQ interrupt sensitive to the following cases:
1. Low level on the IRQ pin.
2. Falling edge on the IRQ pin with all enabled port A interrupt pins at a
high level.
3. Low level on any enabled port A interrupt pin.
4. Falling edge on any enabled port A interrupt pin with all enabled port A
interrupt pins on the IRQ pin at a high level.
This interrupt is serviced by the interrupt service routine located at the address
specified by the contents of $1FFA and $1FFB. The IRQ latch is automatically
Rev. 2.0
4-5
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
