Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Table 4-1. Vector Address for Interrupts and Reset
Register
N/A
Flag Name
N/A
Interrupts
CPU Interrupt
RESET
SWI
Vector Address
$1FFE-$1FFF
$1FFC-$1FFD
$1FFA-$1FFB
$1FF8-$1FF9
$1FF8-$1FF9
$1FF8-$1FF9
Reset
N/A
N/A
Software
N/A
N/A
External Interrupt
Timer Input Capture
Timer Output Capture
Timer Overflow
IRQ
TSR
ICF
TIMER
TIMER
TIMER
TSR
OCF
TSR
TOF
4.1
Hardware Controlled Interrupt Sequence
The following three functions (RESET, STOP, and WAIT) are not interrupts in the
strictest sense. However, they are acted upon in a similar manner. Flowcharts for
hardware interrupts are shown in Figure 4-1, and for STOP and WAIT in Figure 6-
1. A discussion is provided below.
1. RESET — A low input on the RESET input pin causes the program to
vector to its starting address, which is specified by the contents of
memory locations $1FFE and $1FFF. The I bit in the condition code
register also is set. Much of the MCU is configured to a known state
during this type of reset as described in SECTION 5 RESETS.
2. STOP — The STOP instruction causes the oscillator to be turned off and
the processor to "sleep" until an external interrupt (IRQ) or reset
occurs.See 6.1 Stop Mode.
3. WAIT or HALT — The WAIT or HALT instruction causes all processor
clocks to stop, but leaves the timer clock running. This rest state of the
4-2
Rev. 2.0
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