Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
4.4
Optional External Interrupts (PA0-PA7)
The IRQ interrupt can be triggered by the inputs on the PA0 thru PA7 port pins if
enabled by individual mask options. With pullup enabled, each port A pin can
activate the IRQ interrupt function and the interrupt operation will be the same as
for inputs to the IRQ pin. Once enabled by mask option, each individual port A pin
can be disabled as an interrupt source if its corresponding DDR bit is configured
for output mode.
NOTE
The BIH and BIL instructions apply to the output of the logic OR
function of the enabled PA0 thru PA7 interrupt pins and the IRQ pin.
The BIH and BIL instructions to do not exclusively test the state of
the IRQ pin.
NOTE
If enabled, the PA0 thru PA7 pins will cause an IRQ interrupt only if
these individual pins are configured as inputs.
4.5
Software Interrupt (SWI)
The SWI is an executable instruction and a non-maskable interrupt. It is executed
regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts
enabled), SWI executes after interrupts which were pending when the SWI was
fetched but before interrupts generated after the SWI was fetched. The interrupt
service routine address is specified by the contents of memory locations $1FFC
and $1FFD.
4-6
Rev. 2.0
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