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68HC05P4A_1 参数 Datasheet PDF下载

68HC05P4A_1图片预览
型号: 68HC05P4A_1
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 83 页 / 2055 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
GENERAL RELEASE SPECIFICATION  
SECTION 5  
RESETS  
The MCU can be reset three ways: by the initial power-on reset function, by an  
active low input to the RESET pin, and by a computer operating properly (COP)  
watchdog-timer timeout.  
5.1  
Power-On Reset (POR)  
An internal reset is generated on power-up to allow the internal clock generator to  
stabilize. The power-on reset is strictly for power turn-on conditions and should  
not be used to detect a drop in the power supply voltage.  
There is a 4064 internal processor clock cycle (t ) oscillator stabilization delay  
cyc  
after the oscillator becomes active. If the RESET pin is low at the end of this 4064-  
cycle delay, the MCU will remain in the reset condition until RESET goes high.  
5.2  
5.3  
RESET Pin  
The MCU is reset when a logic zero is applied to the RESET input for a period of  
one and one-half machine cycles (t ).  
cyc  
Computer Operating Properly (COP) Reset  
The MCU contains a watchdog timer that automatically times out if not reset  
Rev. 2.0  
5-1  
For More Information On This Product,  
Go to: www.freescale.com  
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