Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
The MCU can be interrupted four different ways: the two maskable hardware
interrupts (IRQ and timer), the non-maskable software interrupt instruction (SWI),
and by the optional external asynchronous interrupt on each port A pin (enabled
by pullup mask option).
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction
causes the register contents to be recovered from the stack and normal
processing to resume.
Unlike RESET, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched and being
operated on.
When the current instruction is complete, the processor checks all pending
hardware interrupts. If interrupts are not masked (CCR I bit clear) and if the
Rev. 2.0
4-1
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