Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
4.3
External Interrupt
The IRQ pin drives an asynchronous interrupt to the CPU. An edge detector flip-
flop is latched on the falling edge of IRQ. If either the output from the internal edge
detector flip-flops or the level on the IRQ pin is low, a request is synchronized to
the CPU to generate the IRQ interrupt. If the edge-sensitive only mask 0ption is
selected, the output of the internal edge detector flip-flop is sampled and the input
level on the IRQ pin is ignored. The interrupt service routine address is specified
by the contents of memory locations $1FFA and $1FFB. A block diagram of the
IRQ function is shown in Figure 4-2.
NOTE
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $1FFA is read). Therefore,
another external interrupt pulse can be latched during the IRQ
service routine.
NOTE
When the edge- and level-sensitive mask option is selected, the
voltage applied to the IRQ pin must return to the high state before
the RTI instruction in the interrupt service routine is executed to
avoid the processor re-entering the IRQ service routine.
IRQ PIN
TO BIH & BIL
INSTRUCTION
SENSING
PA0
DDRA0
4-4
Rev. 2.0
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