Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
t
VDDR
V
Threshold (1-2 V Typical)
DD
V
DD
2
OSC1
t
4064 t
cyc
OXOV
t
cyc
Internal
1
Clock
Internal
Address
New
PC
New
PC
1FFE
1FFF
1FFE
1FFE
1FFE
1FFE
1FFF
PCL
1
Bus
Internal
Data
New
PCH
New
PCL
Op
Code
Op
PCH
PCL
PCH
Code
1
Bus
t
RL
3
RESET
NOTES:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
Figure 5-1. Power-On Reset and RESET
5-2
Rev. 2.0
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