Peripheral Memory Mapped Registers
Table 4-30 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOB_PUR
GPIOB_DR
GPIOB_DDR
GPIOB_PER
$0
$1
$2
$3
0 x 00FF
0 x 0000
0 x 0000
Data Register
Data Direction Register
Peripheral Enable Register
0 x 000F for 20-bit EMI
address at reset.
0 x 0000 for all other cases.
See Table 4-4 for details.
0 x 0000
GPIOB_IAR
$4
$5
$6
$7
$8
$9
$A
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
0 x 0000
0 x 0000
0 x 0000
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
0 x 0000
0 x 0000
—
Table 4-31 GPIOC Registers Address Map
(GPIOC_BASE = $00F310)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOC_PUR
GPIOC_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x 07FF
0 x 0000
0 x 0000
0 x 07FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 07FF
—
Data Register
GPIOC_DDR
GPIOC_PER
GPIOC_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOC_IENR
GPIOC_IPOLR
GPIOC_IPR
GPIOC_IESR
GPIOC_PPMODE
GPIOC_RAWDATA
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
67
FREESCALE [ Freescale ]
