Table 4-27 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F2C0)
Register Acronym
Address Offset
Register Description
COPCTL
COPTO
$0
$1
$2
Control Register
Time Out Register
Counter Register
COPCTR
Table 4-28 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym
PLLCR
Address Offset
Register Description
$0
$1
$2
Control Register
PLLDB
PLLSR
Divide-By Register
Status Register
Reserved
SHUTDOWN
OSCTL
$4
$5
Shutdown Register
Oscillator Control Register
Table 4-29 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Address Offset
Register Description
Reset Value
0 x 3FFF
0 x 0000
0 x 0000
0 x 3FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 3FFF
—
Register Acronym
GPIOA_PUR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Pull-up Enable Register
GPIOA_DR
Data Register
GPIOA_DDR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOA_PER
GPIOA_IAR
GPIOA_IENR
GPIOA_IPOLR
GPIOA_IPR
GPIOA_IESR
GPIOA_PPMODE
GPIOA_RAWDATA
56F8367 Technical Data, Rev. 9
66
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
