Peripheral Memory Mapped Registers
Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued)
(ADCA_BASE = $00 F200)
Register Acronym
Address Offset
$21
Register Description
ADCA_OFS 0
ADCA_OFS 1
ADCA_OFS 2
ADCA_OFS 3
ADCA_OFS 4
ADCA_OFS 5
ADCA_OFS 6
ADCA_OFS 7
ADCA_POWER
ADCA_CAL
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
Offset Register 6
Offset Register 7
$22
$23
$24
$25
$26
$27
$28
$29
$2A
Power Control Register
ADC Calibration Register
Table 4-21 Analog-to-Digital Converter Registers Address Map
(ADCB_BASE = $00 F240)
Register Acronym
Address Offset
Register Description
Control Register 1
ADCB_CR 1
$0
$1
ADCB_CR 2
Control Register 2
ADCB_ZCC
$2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Sample Disable Register
Status Register
ADCB_LST 1
ADCB_LST 2
ADCB_SDIS
$3
$4
$5
ADCB_STAT
ADCB_LSTAT
ADCB_ZCSTAT
ADCB_RSLT 0
ADCB_RSLT 1
ADCB_RSLT 2
ADCB_RSLT 3
ADCB_RSLT 4
ADCB_RSLT 5
ADCB_RSLT 6
ADCB_RSLT 7
ADCB_LLMT 0
$6
$7
Limit Status Register
Zero Crossing Status Register
Result Register 0
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
Result Register 1
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Low Limit Register 0
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
63
FREESCALE [ Freescale ]
