Peripheral Memory Mapped Registers
Table 4-34 GPIOF Registers Address Map
(GPIOF_BASE = $00 F340)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOF_PUR
GPIOF_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x FFFF
0 x 0000
0 x 0000
0 x FFFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x FFFF
—
Data Register
GPIOF_DDR
GPIOF_PER
GPIOF_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOF_IENR
GPIOF_IPOLR
GPIOF_IPR
GPIOF_IESR
GPIOF_PPMODE
GPIOF_RAWDATA
Table 4-35 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym
Address Offset
Register Description
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Pull-up Disable Register
SIM_SCR1
SIM_SCR2
SIM_SCR3
SIM_MSH_ID
SIM_LSH_ID
SIM_PUDR
Reserved
SIM_CLKOSR
SIM_GPS
$A
$B
$C
$D
$E
$F
Clock Out Select Register
Quad Decoder 1 / Timer B / SPI 1 Select Register
Peripheral Clock Enable Register
I/O Short Address Location High Register
I/O Short Address Location Low Register
Peripheral Clock Enable Register 2
SIM_PCE
SIM_ISALH
SIM_ISALL
SIM_PCE2
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
69
FREESCALE [ Freescale ]
