Peripheral Memory Mapped Registers
Table 4-38 FlexCAN Registers Address Map (Continued)
(FC_BASE = $00 F800)
FlexCAN is NOT available in the 56F8167 device
Register Acronym
FCCTL0
Address Offset
Register Description
Control Register 0 Register
$3
$4
$5
$6
FCCTL1
FCTMR
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Reserved
FCMAXMB
FCRXGMASK_H
FCRXGMASK_L
FCRX14MASK_H
FCRX14MASK_L
FCRX15MASK_H
FCRX15MASK_L
$8
$9
$A
$B
$C
$D
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Receive Buffer 15 Mask High Register
Receive Buffer 15 Mask Low Register
Reserved
FCSTATUS
$10
$11
$12
$13
Error and Status Register
FCIMASK1
Interrupt Masks 1 Register
FCIFLAG1
Interrupt Flags 1 Register
FCR/T_ERROR_CNTRS
Receive and Transmit Error Counters Register
Reserved
Reserved
Reserved
FCMB0_CONTROL
FCMB0_ID_HIGH
FCMB0_ID_LOW
FCMB0_DATA
$40
$41
$42
$43
$44
$45
$46
Message Buffer 0 Control / Status Register
Message Buffer 0 ID High Register
Message Buffer 0 ID Low Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Message Buffer 0 Data Register
Reserved
FCMB0_DATA
FCMB0_DATA
FCMB0_DATA
FCMSB1_CONTROL
FCMSB1_ID_HIGH
FCMSB1_ID_LOW
FCMB1_DATA
$48
$49
$4A
$4B
$4C
Message Buffer 1 Control / Status Register
Message Buffer 1 ID High Register
Message Buffer 1 ID Low Register
Message Buffer 1 Data Register
Message Buffer 1 Data Register
FCMB1_DATA
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
71
FREESCALE [ Freescale ]
