Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 10-16 External Memory Interface Timing (Continued)
Wait States
Configuration
Wait States
Controls
Symbol
tARDD
tDRD
D
M
Unit
Characteristic
-2.120
0.00
1.00
N/A1
RWSS,RWS
—
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to RD Deasserted
Valid Input Data Hold after RD
Deasserted
tRD
0.279
1.00
1.00
RWS
RD Assertion Width
-15.723
Address Valid to Input Data Valid
tAD
RWSS,RWS
RWSS
-20.642 1.25 + DCAOE
tARDA
tRDD
tWRRD
tRDRD
-2.603
0.00
1.00
Address Valid to RD Asserted
-13.120
RD Asserted to Input Data Valid
RWSS,RWS
-18.039 1.25 + DCAOE
-2.135 0.25 + DCAEO
WWSH,RWSS
WR Deasserted to RD Asserted
RD Deasserted to RD Asserted
RWSS,RWSH
MDAR3, 4
-0.4832
0.00
WWS=0
WWS>0
WWS=0
WWS>0
-1.608 0.75 + DCAEO
WR Deasserted to WR Asserted
RD Deasserted to WR Asserted
tWRWR
WWSS, WWSH
ns
ns
-0.918
-0.096
1.00
0.50
RWSH, WWSS,
MDAR3
tRDWR
0.084 0.75 + DCAOE
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, and the chip select does not change, then RD does not deassert during back-to-back reads.
3. Substitute BMDAR for MDAR if there is no chip select
4. MDAR is active in this calculation only when the chip select changes.
10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
Characteristic
Symbol
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
10-6
Minimum RESET Assertion Duration
tRA
16T
63T
—
ns
ns
10-6
10-6
RESET Deassertion to First External Address
Output3
tRDA
64T
Edge-sensitive Interrupt Request Width
tIRW
tIDM
1.5T
18T
14T
—
—
—
ns
ns
10-7
10-8
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
tIDM - FAST
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
151
FREESCALE [ Freescale ]
