10.10 Serial Peripheral Interface (SPI) Timing
1
Table 10-18 SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
10-11, 10-12,
10-13, 10-14
50
50
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
10-14
10-14
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCK) high time
Master
Slave
10-11, 10-12,
10-13, 10-14
17.6
25
—
—
ns
ns
Clock (SCK) low time
Master
Slave
10-14
24.1
25
—
—
ns
ns
Data set-up time required for inputs
Master
Slave
tDS
tDH
tA
10-11, 10-12,
10-13, 10-14
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
10-11, 10-12,
10-13, 10-14
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
10-14
10-14
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
10-11, 10-12,
10-13, 10-14
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
10-11, 10-12,
0
0
—
—
ns
ns
10-13
Rise time
Master
Slave
10-11, 10-12,
10-13, 10-14
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
10-11, 10-12,
10-13, 10-14
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F8367 Technical Data, Rev. 9
154
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
