VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tfall
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-4 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-14 PLL Timing
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
Unit
MHz
MHz
External reference crystal frequency for the PLL1
8.4
PLL output frequency2 (fOUT
)
fop
160
—
260
PLL stabilization time3 -40° to +125°C
tplls
—
1
10
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (f
/2), please refer to the OCCS chapter in
OUT
the 56F8300 Peripheral User Manual.
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
10.7 Crystal Oscillator Timing
Table 10-15 Crystal Oscillator Parameters
Characteristic
Crystal Start-up time
Symbol
TCS
Min
4
Typ
5
Max
10
Unit
ms
ms
ohms
ps
Resonator Start-up time
TRS
0.1
—
0.18
—
1
Crystal ESR
RESR
TD
120
250
1.5
300
300
290
110
Crystal Peak-to-Peak Jitter
Crystal Min-Max Period Variation
Resonator Peak-to-Peak Jitter
Resonator Min-Max Period Variation
Bias Current, high-drive mode
Bias Current, low-drive mode
70
0.12
—
—
TPV
—
ns
TRJ
—
ps
TRP
—
—
ps
IBIASH
IBIASL
—
250
80
μA
—
μA
56F8367 Technical Data, Rev. 9
148
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
