1,2
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Typical
Min
Typical
Max
Characteristic
Symbol
Unit
See Figure
IRQA, IRQB Assertion to General Purpose
Output Valid, caused by first instruction
execution in the interrupt service routine
tIG
tIG - FAST
tIRI
18T
14T
22T
18T
22T
18T
1.5T
—
—
—
—
—
—
—
ns
10-8
10-9
Delay from IRQA Assertion (exiting Wait) to
External Data Memory Access4
ns
ns
ns
tIRI -FAST
tIF
Delay from IRQA Assertion to External Data
Memory Access (exiting Stop)
10-10
10-10
tIF - FAST
tIW
IRQA Width Assertion to Recover from Stop
State5
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and
Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
21
3. During Power-On Reset, it is possible to use the device’s internal reset stretching circuitry to extend this period to 2 T.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This
is not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
RESET
tRA
tRAZ
tRDA
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
First Fetch
Figure 10-6 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 10-7 External Interrupt Timing (Negative Edge-Sensitive)
56F8367 Technical Data, Rev. 9
152
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
