External Memory Interface Timing
Table 10-15 Crystal Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Quiescent Current, power-down mode
IPD
—
0
1
μA
10.8 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-5
shows sample timing and parameters that are detailed in Table 10-16.
The timing of each parameter consists of both a fixed delay portion and a clock related portion, as well as
user controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in this equation are defined as:
t
= Parameter delay time
D
P
= Fixed portion of the delay, due to on-chip path delays
= Period of the system clock, which determines the execution rate of the part
(i.e., when the device is operating at 60MHz, P = 16.67 ns)
M
W
= Fixed portion of a clock period inherent in the design; this number is adjusted to account
for possible derating of clock duty cycle
= Sum of the applicable wait state controls. The “Wait State Controls” column of
Table 10-16 shows the applicable controls for each parameter and the EMI chapter of
the 56F8300 Peripheral User Manual details what each wait state field controls.
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler set to 1), the EMI quadrature clock is generated using both edges of the EXTAL clock
÷
input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE and
DCAEO are used to make this duty cycle adjustment where needed.
DCAOE and DCAEO are calculated as follows:
DCAOE = 0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to
= 0.0 all other cases
÷
÷
1
1
DCAEO = MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to
= 0.0 all other cases
Example of DCAOE and DCAEO calculation:
Assuming prescaler is set for
÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high;
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of Table 10-16 to make the appropriate selection.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
149
FREESCALE [ Freescale ]
