A0-Axx,CS
tRD
tARDD
tRDA
tRDRD
tARDA
RD
tWAC
tWRRD
tAWR
tWRWR
tWR
tRDWR
WR
tDWR
tDOH
tRDD
tDOS
Data Out
tAD
tDRD
Data In
D0-D15
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 10-5 External Memory Interface Timing
Note:
When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
Table 10-16 External Memory Interface Timing
Wait States
Configuration
Wait States
Controls
Symbol
tAWR
D
M
Unit
ns
Characteristic
WWS=0
WWS>0
WWS=0
WWS>0
WWS=0
WWS=0
WWS>0
WWS>0
-2.076
0.50
Address Valid to WR Asserted
WWSS
WWS
-1.795 0.75 + DCAOE
-0.094 0.25 + DCAOE
WR Width Asserted to WR
Deasserted
tWR
ns
-0.012
0
-9.321 0.25 + DCAEO
Data Out Valid to WR Asserted
-1.160
-8.631
0.00
0.50
tDWR
WWSS
ns
-0.879 0.25 + DCAOE
-2.086 0.25 + DCAEO
-0.563 0.25 + DCAOE
Valid Data Out Hold Time after WR
Deasserted
tDOH
WWSH
ns
ns
Valid Data Out Set-Up Time to WR
Deasserted
tDOS
WWS,WWSS
-8.315
-3.432 0.25 + DCAEO
-1.780 0.00
0.50
tWAC
tRDA
WWSH
RWSH
ns
ns
Valid Address after WR Deasserted
RD Deasserted to Address Invalid
56F8367 Technical Data, Rev. 9
150
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
