JTAG Timing
Table 10-22 JTAG Timing
Characteristic
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
Symbol
tDV
Min
—
Max
30
Unit
ns
See Figure
10-19
10-19
10-20
tTS
—
30
ns
2T2
tTRST
—
ns
1. TCK frequency of operation must be less than 1/8 the processor rate.
2. T = processor clock period (nominally 1/60MHz)
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-18 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
tDV
TDO
(Output)
Output Data Valid
Figure 10-19 Test Access Port Timing Diagram
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
151
FREESCALE [ Freescale ]
