Register Descriptions
6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.12 Stop Disable Register 1 (SD1)
See Section 6.3.11 for general information about Stop Disable Registers.
Base + $F
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PIT2_ PIT1_
SD
PIT0_
SD
TA3_
SD
TA2_ TA1_ TA0_
SD
SD
SD
SD
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-13 Stop Disable Register 1 (SD1)
6.3.12.1 Reserved—Bit 15
This bit field is reserved. It must be set to 0.
6.3.12.2 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.3 Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.4 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.5 Reserved—Bits 11–4
This bit field is reserved. Each bit must be set to 0.
6.3.12.6 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
93
FREESCALE [ Freescale ]
