6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.5 Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.11.6 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.7 Reserved—Bits 9–7
This bit field is reserved. It must be set to 0.
6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.9 Reserved—Bit 5
This bit field is reserved. It must be set to 0.
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.11 Reserved—Bit 3
This bit field is reserved. It must be set to 0.
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.13 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
56F8036 Data Sheet, Rev. 6
92
FreescaleSemiconductor
FREESCALE [ Freescale ]
