Register Descriptions
6.3.1
SIM Control Register (SIM_CTRL)
Base + $0
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
ONCE SW
EBL
STOP_
DISABLE
WAIT_
DISABLE
RST
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-2 SIM Control Register (SIM_CTRL)
6.3.1.1
Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
6.3.1.2
OnCE Enable (ONCEEBL)—Bit 5
•
•
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Note:
Using default state “0” is recommended.
6.3.1.3
Software Reset (SWRST)—Bit 4
•
•
Writing 1 to this field will cause the device to reset
Read is 0
6.3.1.4
Stop Disable (STOP_DISABLE)—Bits 3–2
•
•
•
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
•
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
6.3.1.5
Wait Disable (WAIT_DISABLE)—Bits 1–0
•
•
•
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
•
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
6.3.2
SIM Reset Status Register (SIM_RSTAT)
This read-only register is updated upon any system reset and indicates the cause of the most recent reset.
It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External
Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On
Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
83
FREESCALE [ Freescale ]
