Add.
Address
Offset Acronym
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
SIM_
CTRL
ONCE SW
EBL0 RST
STOP_
DISABLE
WAIT_
DISABLE
$0
W
COP_ COP_
R
0
0
0
0
0
0
0
0
0
SWR
EXTR POR
0
0
SIM_
$1
TOR
LOR
RSTAT
W
R
$2
$3
$4
$5
$6
$7
$8
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
Software Control Data 0
Software Control Data 1
Software Control Data 2
Software Control Data 3
W
R
W
R
W
R
W
R
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
W
R
W
R
SIM_PWR
Reserved
LRSTDBY
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
CLKOUT
$A
$B
$C
$D
$E
$F
PWM3 PWM2 PWM1 PWM0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TMRA_ PWM_C I2C_
CR CR
SIM_PCR
SIM_PCE0
SIM_PCE1
SIM_SD0
SIM_SD1
R
W
R
CMPB CMPA DAC1 DAC0
0
ADC
0
I2C
0
QSCI0
0
QSPI0
TA2
PWM
TA0
W
R
PIT2
PIT1
PIT0
TA3
0
TA1
0
W
R
CMPB_ CMPA_ DAC1_ DAC0_
SD
ADC_
SD
I2C_
SD
QSCI0
_SD
QSPI0
_SD
PWM_
SD
SD
SD
SD
W
R
0
0
0
0
PIT2_ PIT1_S PIT0_
TA3_ TA2_ TA1_ TA0_
SD
SD
0
D
0
SD
0
SD
SD
SD
W
R
0
0
0
0
0
0
$10 SIM_IOSAHI
$11 SIM_IOSALO
ISAL[23:22]
W
R
ISAL[21:6]
0
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$12
SIM_PROT
PCEP
GIPSP
W
R
0
0
0
0
GPS_
A6
$13 SIM_GPSA0
$14 SIM_GPSA1
$15 SIM_GPSB0
$16 SIM_GPSB1
$17 SIM_GPSCD
GPS_A5
GPS_A4
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_A9
GPS_A8
W
R
0
0
0
0
0
0
GPS_
B1
GPS_
B0
GPS_B6
GPS_B5
GPS_B3
GPS_B2
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_
B9
GPS_
B8
GPS_
B7
W
R
0
0
0
GPS_
D5
W
R
0
IPS0_
FAULT2
IPS0_
FAULT1
$18
$19
$1A
SIM_IPS0
SIM_IPS1
IPS0_PSRC2
0
IPS0_PSRC1
IPS0_PSRC0
W
R
0
0
0
0
0
0
0
0
IPS1_DSYNC1
IPS1_DSYNC0
0 0
W
R
0
0
0
0
IPS2_
TA3
IPS2_
TA2
IPS2_
TA1
SIM_IPS2
Reserved
W
0
= Read as 0
1
= Read as 1
= Reserved
Figure 6-1 SIM Register Map Summary
56F8036 Data Sheet, Rev. 6
82
FreescaleSemiconductor
FREESCALE [ Freescale ]
