5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.19.5 Reserved—Bits 4-2
This bit field is reserved. Each bit must be set to 1.
5.6.19.6 Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
5.7 Resets
5.7.1
General
Table 5-5 Reset Summary
Source
Characteristics
Reset
Priority
Core Reset
RST
Core reset from the SIM
5.7.2
Description of Reset Operation
Reset Handshake Timing
5.7.2.1
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-22.
RES
CLK
RESET_VECTOR_ADR
VAB
PAB
READ_ADR
Figure 5-22 Reset Interface
56F8036 Data Sheet, Rev. 6
78
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