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56F8036_10 参数 Datasheet PDF下载

56F8036_10图片预览
型号: 56F8036_10
PDF下载: 下载PDF文件 查看货源
内容描述: 16位数字信号控制器 [16-bit Digital Signal Controllers]
分类和应用: 控制器
文件页数/大小: 164 页 / 893 K
品牌: FREESCALE [ Freescale ]
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Register Descriptions  
5.6.4.2  
Reserved—Bits 13–6  
This bit field is reserved. Each bit must be set to 0.  
5.6.4.3  
QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)—Bits 5–4  
This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited  
to priorities 0 through 2. It is disabled by default.  
00 = IRQ disabled (default)  
01 = IRQ is priority level 0  
10 = IRQ is priority level 1  
11 = IRQ is priority level 2  
5.6.4.4  
QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)—  
Bits 3–2  
This field is used to set the interrupt priority level for the QSCI0 Receiver Error IRQ. This IRQ is limited  
to priorities 0 through 2. It is disabled by default.  
00 = IRQ disabled (default)  
01 = IRQ is priority level 0  
10 = IRQ is priority level 1  
11 = IRQ is priority level 2  
5.6.4.5  
QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)—  
Bits 1–0  
This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited  
to priorities 0 through 2. It is disabled by default.  
00 = IRQ disabled (default)  
01 = IRQ is priority level 0  
10 = IRQ is priority level 1  
11 = IRQ is priority level 2  
5.6.5  
Interrupt Priority Register 4 (IPR4)  
Base + $4  
Read  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
TMRA_3 IPL  
TMRA_2 IPL  
TMRA_1 IPL  
TMRA_0 IPL I2C_STAT IPL I2C_TX IPL  
I2C_RX IPL I2C_GEN IPL  
Write  
RESET  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-7 Interrupt Priority Register 4 (IPR4)  
56F8036 Data Sheet, Rev. 6  
Freescale Semiconductor  
67  
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