Peripheral Memory-Mapped Registers
2
Table 4-28 I C Registers Address Map
(I2C_BASE = $00 F280)
Register Acronym
Address Offset
Register Description
I2C_CTRL
I2C_TAR
I2C_SAR
I2C_DATA
$0
$2
Control Register
Target Address Register
Slave Address Register
$4
$8
RX/TX Data Buffer and Command Register
Standard Speed Clock SCL High Count Register
Standard Speed Clock SCL Low Count Register
Fast Speed Clock SCL High Count Register
Fast Speed Clock SCL Low Count Register
Interrupt Status Register
I2C_SSHCNT
I2C_SSLCNT
I2C_FSHCNT
I2C_FSLCNT
I2C_ISTAT
$A
$C
$E
$10
$16
$18
$1A
$1C
$1E
$20
$22
$24
$26
$28
$2A
$2C
$2E
$30
$32
$34
$36
$38
$3A
$3C
$40
I2C_IMASK
Interrupt Mask Register
I2C_RISTAT
Raw Interrupt Status Register
I2C_RXFT
Receive FIFO Threshold Register
Transmit FIFO Threshold Register
Clear Combined and Individual Interrupts Register
Clear RX_UNDER Interrupt Register
Clear RX_OVER Interrupt Register
Clear TX_OVER Interrupt Register
Clear RD_REQ Interrupt Register
Clear TX_ABRT Interrupt Register
Clear RX_DONE Interrupt Register
Clear Activity Interrupt Register
Clear STOP_DET Interrupt Register
Clear START_DET Interrupt Register
Clear GEN_CALL Interrupt Register
Enable Register
I2C_TXFT
I2C_CLRINT
I2C_CLRRXUND
I2C_CLRRXOVR
I2C_CLRTXOVR
I2C_CLRRDREQ
I2C_CLRTXABRT
I2C_CLRRXDONE
I2C_CLRACT
I2C_CLRSTPDET
I2C_CLRSTDET
I2C_CLRGC
I2C_ENBL
I2C_STAT
Status Register
I2C_TXFLR
Transmit FIFO Level Register
I2C_RXFLR
Receive FIFO Level Register
I2C_TXABRTSRC
Transmit Abort Status Register
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
53