3.7 Serial Peripheral Interface (SPI) Timing
1
Table 3-12 SPI Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
Figures 3-19, 3-20,
3-21, 3-22
50
25
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
Figure 3-22
Figure 3-22
—
25
—
—
ns
ns
Enable lag time
Master
Slave
—
100
—
—
ns
ns
Clock (SCK) high time
Master
Slave
Figures 3-19, 3-20,
3-21, 3-22
17.6
12.5
—
—
ns
ns
Clock (SCK) low time
Master
Slave
Figures 3-19, 3-20,
3-21, 3-22
24.1
25
—
—
ns
ns
Data setup time required for inputs
Master
Slave
tDS
tDH
tA
Figures 3-19, 3-20,
3-21, 3-22
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
Figures 3-19, 3-20,
3-21, 3-22
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
Figure 3-22
Figure 3-22
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
Figures 3-19, 3-20,
3-21, 3-22
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
Figures 3-19, 3-20,
3-21, 3-22
0
0
—
—
ns
ns
Rise time
Master
Slave
Figures 3-19, 3-20,
3-21, 3-22
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
Figures 3-19, 3-20,
3-21, 3-22
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F801 Technical Data, Rev. 17
32
Freescale Semiconductor
FREESCALE [ Freescale ]
