SS
(Input)
tC
tF
tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tCL
tELD
SCLK (CPOL = 1)
(Input)
tCH
tA
tR
tF
tD
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 3-21 SPI Slave Timing (CPHA = 0)
SS
(Input)
tC
tF
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tCL
tELG
tELD
SCLK (CPOL = 1)
(Input)
tDV
tR
tCH
tD
tF
tA
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 3-22 SPI Slave Timing (CPHA = 1)
56F801 Technical Data, Rev. 17
34
Freescale Semiconductor
FREESCALE [ Freescale ]
