Quad Timer Timing
3.8 Quad Timer Timing
1, 2
Table 3-13 Timer Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Timer input period
Symbol
PIN
Min
4T+6
2T+3
2T
Max
—
Unit
ns
Timer input high/low period
Timer output period
PINHL
POUT
—
ns
—
ns
Timer output high/low period
POUTHL
1T
—
ns
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PIN
PINHL
PINHL
Timer Outputs
POUT
POUTHL
POUTHL
Figure 3-23 Timer Timing
3.9 Serial Communication Interface (SCI) Timing
4
Table 3-14 SCI Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
—
Max
Unit
Baud Rate1
BR
(fMAX*2.5)/(80)
Mbps
RXD2 Pulse Width
TXD3 Pulse Width
RXDPW
TXDPW
0.965/BR
1.04/BR
1.04/BR
ns
ns
0.965/BR
1. fMAX is the frequency of operation of the system clock in MHz.
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
56F801 Technical Data, Rev. 17
Freescale Semiconductor
35
FREESCALE [ Freescale ]
