RESET
tRA
tRAZ
tRDA
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
First Fetch
Figure 3-13 Asynchronous Reset Timing
IRQA,
IRQB
tIRW
Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive)
A0–A15,
PS, DS,
RD, WR
First Interrupt Instruction Execution
tIDM
IRQA,
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
tIG
IRQA,
IRQB
b) General Purpose I/O
Figure 3-15 External Level-Sensitive Interrupt Timing
56F801 Technical Data, Rev. 17
30
Freescale Semiconductor