Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—
21
ns
Figure 3-13
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
Figure 3-13
Figure 3-13
275,000T
128T
—
—
ns
ns
RESET De-assertion to First External Address
Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
tIDM
1.5T
15T
—
—
ns
ns
Figure 3-14
Figure 3-15
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
Figure 3-15
Figure 3-16
IRQA Low to First Valid Interrupt Vector Address
Out recovery from Wait State3
tIRI
13T
2T
—
—
ns
ns
IRQA Width Assertion to Recover from Stop State4
tIW
tIF
Figure 3-17
Figure 3-17
Delay from IRQA Assertion to Fetch of first
instruction (exiting Stop)
OMR Bit 6 = 0
—
—
275,000T
12T
ns
ns
OMR Bit 6 = 1
Duration for Level Sensitive IRQA Assertion to
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
Figure 3-18
Figure 3-18
—
—
275,000T
12T
ns
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
tII
—
—
275,000T
12T
ns
ns
OMR Bit 6 = 1
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
56F801 Technical Data, Rev. 17
Freescale Semiconductor
29
FREESCALE [ Freescale ]
