3.5.5
Phase Locked Loop Timing
Table 3-10 PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Symbol
Min
4
Typ
8
Max
Unit
MHz
MHz
ms
External reference crystal frequency for the PLL1
PLL output frequency2
fosc
10
803
—
f
out/2
tplls
40
—
—
—
PLL stabilization time4 0o to +85oC
PLL stabilization time4 -40o to 0oC
10
tplls
100
200
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. Will not exceed 60MHz for the DSP56F801FA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
56F801 Technical Data, Rev. 17
28
Freescale Semiconductor
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