Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tF
tCH
tCL
tR
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
tDV
MOSI
(Output)
Master MSB out
tF
Bits 14–1
Master LSB out
tR
Figure 3-19 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tCL
tF
SCLK (CPOL = 1)
(Output)
tCH
tDS
tR
tDH
MISO
(Input)
MSB in
tDI
Bits 14–1
LSB in
tDV
tDV(ref)
MOSI
(Output)
Master MSB out
tF
Bits 14– 1
Master LSB out
tR
Figure 3-20 SPI Master Timing (CPHA = 1)
56F801 Technical Data, Rev. 17
Freescale Semiconductor
33
FREESCALE [ Freescale ]
