compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the
resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not
switched until the desired clock is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within ±0.25% of 8MHz by trimming an internal capacitor. Bits 0-7 of
the IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this
preset value to increase or decrease capacitance. The default value of this trim is 128 units, making the
power-up default capacitor size 432 units. Each unit added or deleted changes the output frequency by
about 0.2%, allowing incremental adjustment until the desired frequency accuracy is achieved.
Table 3-9 Relaxation Oscillator Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic
Frequency Accuracy1
Symbol
Δf
Min
—
Typ
+2
Max
+5
Unit
%
%/oC
%/V
%
Frequency Drift over Temp
Frequency Drift over Supply
Δf/Δt
—
+0.1
—
Δf/ΔV
ΔfT
—
—
0.1
—
—
Trim Accuracy
+0.25
1. Over full temperature range.
56F801 Technical Data, Rev. 17
26
Freescale Semiconductor
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