Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The System Integration Module
is responsible for the following functions:
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Reset sequencing
Clock control & distribution
Stop/Wait control
System status registers
Registers for software access to the JTAG ID of the chip
Test registers
Power control
I/O pad multiplexing
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
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System bus clocks with pipeline hold-off support
System clocks for non-pipelined interfaces
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Peripheral clocks for TMR and PWM with high-speed (3X) option
Power-saving clock gating for peripherals
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ITCK clock to the 56800E core TAP interface
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full part operation
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Controls, with write protection, the enable/disable of 56800E core WAIT and STOP instructions
Controls, with write protection, the enable/disable of Large Regulator Standby mode
Controls to route functional signals to selected peripherals and I/O pads
Controls deassertion sequence of internal resets
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general-purpose software control
Timer channel Stop mode clocking controls
SCI Stop mode clocking control to support LIN Sleep mode stop recovery
Short addressing location control
Registers for software access to the JTAG ID of the chip
Controls output to CLKO pin
56F8014 Technical Data, Rev. 9
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Freescale Semiconductor
Preliminary
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