5.6.11 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Base + $A
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FAST INTERRUPT 1 VECTOR ADDRESS LOW
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.11.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.12 Fast Interrupt 1 Vector Address High Register (FIVAH1)
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.12.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.12.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.13 IRQ Pending Register 0 (IRQP0)
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING[16:2]
Write
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-15 IRQ Pending Register 0 (IRQP0)
5.6.13.1 IRQ Pending (PENDING)—Bits 15–1
This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.13.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
56F8014 Technical Data, Rev. 9
58
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
