Resets
5.7 Resets
5.7.1
General
Table 5-4 Reset Summary
Source
Characteristics
Reset
Priority
Core Reset
RST
Core reset from the SIM
5.7.2
Description of Reset Operation
Reset Handshake Timing
5.7.2.1
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-19 .
RES
CLK
RESET_VECTOR_ADR
VAB
PAB
READ_ADR
Figure 5-19 Reset Interface
5.7.3
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
•
•
•
•
•
•
•
•
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
61
FREESCALE [ Freescale ]
