Register Descriptions
5.6.14 IRQ Pending Register 1 (IRQP1)
Base + $D
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING[32:17]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-16 IRQ Pending Register 1 (IRQP1)
5.6.14.1 IRQ Pending (PENDING)—Bits 32–17
This register combines with IRQP0 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.15 IRQ Pending Register 2 (IRQP2)
Base + $E
Read
15
1
14
1
13
1
12
11
10
9
8
1
7
6
5
4
1
3
1
2
1
1
1
0
1
PENDING[45:33]
Write
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-17 IRQ Pending Register 2 (IRQP2)
5.6.15.1 IRQ Pending (PENDING)—Bits 45–33
This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers
2 through 45.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.16 Interrupt Control Register (ICTRL)
$Base + $12
Read
15
14
13
12
11
10
9
8
7
0
6
0
5
4
1
3
1
2
1
1
0
0
0
INT
IPIC
VAB
INT_
DIS
Write
0
0
0
0
0
0
0
0
0
1
1
1
0
0
RESET
Figure 5-18 Interrupt Control Register (ICTRL)
5.6.16.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
•
•
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
56F8014 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
59
FREESCALE [ Freescale ]
